User:Sayantanghosh2024

Sayantan

I am a Physical Design Engineer with expertise in VLSI design, physical implementation, and layout design across advanced technology nodes. With over a decade of experience, I have contributed to multiple tape-outs, specializing in floorplanning, clock tree synthesis, routing, power delivery networks, timing closure, and static timing analysis in 4nm, 7nm, 12nm, and 14nm technologies.

I am currently pursuing master’s in Electrical and Computer Engineering from the University of Minnesota, Twin Cities, and I hold bachelor’s degree in Electronics and Communication Engineering. Beyond industry contributions, I am actively involved in research on AI hardware acceleration and heterogeneous SoC RISC-V design, along with mentoring students in VLSI design. My expertise includes EDA tools, scripting, and low-power design, focusing on advanced semiconductor processes.

I have created this page for my class assignment for the subject - CSCI 5125: Collaborative and Social Computing.