Talk:Decimal128 floating-point format

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G Combination field for BID vs DPD

The G combination field encodes exponent + hi 4 bits of significand + special values. The article currently describes one encoding/layout for the G combination field at the beginning of the article and seems to imply that this bit layout applies to both BID and DPD significand format.

In fact IEEE 754-2008/2019 specifies two different bit layouts for the G combination field for BID vs DPD formats. The G combination field is described again under the "significand field" descriptions, but those sections are really describing more than just the significand field.

The existing table showing G combination field is a good presentation and makes it understandable, but it only applies to the BID format.

I'm not an experienced wikipedia editor, so looking for guidance/assistance/encouragement.

Proposed fix:

Move the current G combination field layout table under BID, incorporating existing G combination field description under BID
Add a parallel layout table under DPD encoding

Sources:

IEEE Std 754-2019, section [3.5.2] Encodings, pages 20-21
IEEE Std 754-2008, section [3.5.2] Encodings, pages 10-11

MiguelDecimal128 (talk) 11:18, 1 September 2025 (UTC)[reply]