Minimal instruction set computer

Minimal instruction set computer (MISC) is a central processing unit (CPU) architecture, usually in the form of a microprocessor, with a very small number of basic operations and corresponding opcodes, together forming an instruction set. Such sets are commonly stack-based rather than register-based to reduce the size of operand specifiers.

Such a stack machine architecture is inherently simpler since all instructions operate on the top-most stack entries.

One result of the stack architecture is an overall smaller instruction set, allowing a smaller and faster instruction decode unit with overall faster operation of individual instructions.

Characteristics and design philosophy

Separate from the stack definition of a MISC architecture, is the MISC architecture being defined by the number of instructions supported.

Typically a minimal instruction set computer is viewed as having 32 or fewer instructions,^[1]^[2]^[3] where NOP, RESET, and CPUID type instructions are usually not counted by consensus due to their fundamental nature.
32 instructions is viewed as the highest allowable number of instructions for a MISC^{[by whom?]}, though 16 or 8 instructions are closer to what is meant by "Minimal Instructions".
A MISC CPU cannot have zero instructions as that is a zero instruction set computer.
A MISC CPU cannot have one instruction as that is a one instruction set computer.^[4]
The implemented CPU instructions should by default not support a wide set of inputs, so this typically means an 8-bit or 16-bit CPU.^{[citation needed]}
If a CPU has an NX bit, it is more likely to be viewed as being a complex instruction set computer (CISC) or reduced instruction set computer (RISC).
MISC chips typically lack hardware memory protection of any kind, unless there is an application specific reason to have the feature.
If a CPU has a microcode subsystem, that excludes it from being a MISC.^{[citation needed]}

Also, the instruction pipelines of MISC as a rule tend to be very simple. Instruction pipelines, branch prediction, out-of-order execution, register renaming, and speculative execution broadly exclude a CPU from being classified as a MISC architecture.^{[citation needed]}

While 1-bit CPUs are otherwise obsolete (and were not MISCs nor OISCs), the first carbon nanotube computer is a 1-bit one-instruction set computer, and has only 178 transistors, and thus likely the lowest-complexity (or next-lowest) CPU produced so far (by transistor count).

Example CPUs

Tube-based processors

Some of the first tube-based digital computers implemented with instruction sets are by modern definition minimal instruction set computers. All are serial computers except for Whirlwind.

Manchester Baby (University of Manchester, England) made its first successful run of a stored program on June 21, 1948. It supported seven instructions.
Electronic Delay Storage Automatic Calculator (EDSAC, University of Cambridge, England) was the first practical stored-program electronic computer (May 1949). It had twelve instructions.
Manchester Mark 1 (Victoria University of Manchester, England) Developed from the Baby (June 1949). It had 30 instructions.
Electronic Discrete Variable Automatic Computer (EDVAC, Ballistic Research Laboratory, Computing Laboratory at Aberdeen Proving Ground 1951). It had twelve instructions.
The Standards Eastern Automatic Computer (SEAC) was demonstrated in April 1950. It had eleven instructions.
MESM performed its first test run in Kyiv on November 6, 1950. It had ten instructions.
The Whirlwind was completed in December 1950 and was in actual use in April 1951. It had 27 instructions.
Librascope LGP-30 is an mass-produced desk-sized computer introduced in 1956. It has sixteen instructions.

Integrated circuit processors

Probably the most commercially successful MISC was the original Inmos transputer architecture that has no floating-point unit. It has sixteen primary and sixteen secondary instructions.

The Signetics 8X300 is an 8-bit microprocessor introduced in 1976. It has eight instructions.

Each STEREO spacecraft includes two P24 MISC CPUs and two CPU24 soft processors.^[5]^[6]^[7]^[8]

Design weaknesses

The disadvantage of a MISC is that instructions tend to have more sequential dependencies, reducing overall instruction-level parallelism.^{[citation needed]}

MISC architectures have much in common with some features of some programming languages such as Forth's use of the stack, and the Java virtual machine. Both are weak in providing full instruction-level parallelism. However, one could employ macro-op fusion as a means of executing common instruction phrases as individual steps (e.g., ADD,FETCH to perform a single indexed memory read).

References

^ Ting, Chen-hanson; Moore, Charles H. (1995). "MuP21: A High Performance MISC Processor". UltraTechnology. Offete Enterprises.
^ US patent 5481743A, Baxter, Michael A., "Minimal instruction set computer architecture and multiple instruction issue method", published 1996-01-02, issued 1996-01-02, assigned to Apple
^ Halverson, Richard Jr.; Lew, Art (1995). An FPGA-Based Minimal Instruction Set Computer (Technical report). Information and Computer Sciences Department, University of Hawai. p. 23. ICS-TR-94-28.
^ Kong, J.H.; Ang, L.-M.; Seng, K.P. (2010). "Minimal Instruction Set AES Processor using Harvard Architecture". 2010 3rd International Conference on Computer Science and Information Technology. pp. 65–69. doi:10.1109/ICCSIT.2010.5564522. ISBN 978-1-4244-5540-9.
^ Mewaldt, R. A.; Cohen, C. M. S.; Cook, W. R.; Cummings, A. C.; et al. "3.5.2 The Minimal Instruction Set Computer (MISC)". The Low-Energy Telescope (LET) and SEP Central Electronics for the STEREO Mission (PDF) (Report). p. 20. Archived from the original (PDF) on 2020-10-11.
^ Russell, C.T., ed. (2008). The STEREO Mission. Springer. ISBN 978-0-387-09649-0.
^ Ting, C-H; Cook, W.R. (2001). P24 MISC Microprocessor User's Manual (Technical report). eMAST Technology. STEREO-CIT-005.A.
^ CPU24 Microprocessor User's Manual (Technical report). NASA. October 2003. Version 5 Actel for Stereo HET.

External links

Forth MISC chip designs
seaForth-24 – the next to latest multi-core processor MISC design from Charles H. Moore
Green Arrays - the latest multi-core processor MISC design from Charles H. Moore

[1] Ting, Chen-hanson; Moore, Charles H. (1995). "MuP21: A High Performance MISC Processor". UltraTechnology. Offete Enterprises.

[2] US patent 5481743A, Baxter, Michael A., "Minimal instruction set computer architecture and multiple instruction issue method", published 1996-01-02, issued 1996-01-02, assigned to Apple

[3] Halverson, Richard Jr.; Lew, Art (1995). An FPGA-Based Minimal Instruction Set Computer (Technical report). Information and Computer Sciences Department, University of Hawai. p. 23. ICS-TR-94-28.

[4] Kong, J.H.; Ang, L.-M.; Seng, K.P. (2010). "Minimal Instruction Set AES Processor using Harvard Architecture". 2010 3rd International Conference on Computer Science and Information Technology. pp. 65–69. doi:10.1109/ICCSIT.2010.5564522. ISBN 978-1-4244-5540-9.

[5] Mewaldt, R. A.; Cohen, C. M. S.; Cook, W. R.; Cummings, A. C.; et al. "3.5.2 The Minimal Instruction Set Computer (MISC)". The Low-Energy Telescope (LET) and SEP Central Electronics for the STEREO Mission (PDF) (Report). p. 20. Archived from the original (PDF) on 2020-10-11.

[6] Russell, C.T., ed. (2008). The STEREO Mission. Springer. ISBN 978-0-387-09649-0.

[7] Ting, C-H; Cook, W.R. (2001). P24 MISC Microprocessor User's Manual (Technical report). eMAST Technology. STEREO-CIT-005.A.

[8] CPU24 Microprocessor User's Manual (Technical report). NASA. October 2003. Version 5 Actel for Stereo HET.

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