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Català: Estructura esquemàtica d'un xip CMOS, tal com es va construir a principis dels anys 2000. El gràfic mostra els LDD-MISFET sobre un substrat de silici SOI amb cinc capes de metal·lització i un tap de soldadura per a la unió de xip. També mostra la secció per a FEOL (front-end de línia), BEOL (back-end de línia) i les primeres parts del procés de back-end. (versió traduïda a l'alemany)
English: Schematic structure of a CMOS chip, like it is built in the early 2000s. The graphic shows LDD-MISFET's on a SOI silicon substrate with five metallization layers and solder bump for flip-chip bonding. Also it shows the section for FEOL (front-end of line), BEOL (back-end of line) and first parts of back-end process. Self made from university scripts and scientific papers
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Cmos-chip structure in 2000s (en).svg (Catalan)
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In dieser Datei abgebildete Objekte

depicts

MOSFET

inception

9 December 2006

media type

image/svg+xml

checksum

98b4a7c115393efaade08e41f7203a44dae22f52

determination method or standard: SHA-1

data size

140,823 byte

height

810 pixel

width

550 pixel

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Date/TimeThumbnailDimensionsUserComment
current14:35, 5 February 2024Thumbnail for version as of 14:35, 5 February 2024550 × 810 (138 KB)ManlleusFile uploaded using svgtranslate tool (https://svgtranslate.toolforge.org/). Added translation for ca.
14:25, 5 February 2024Thumbnail for version as of 14:25, 5 February 2024550 × 810 (97 KB)Manlleusfixed text labels for translation
18:52, 9 December 2006Thumbnail for version as of 18:52, 9 December 2006550 × 810 (85 KB)Cepheiden{{Information |Description= Schematic structure of a CMOS chip, like it is build in the early 2000s. The grafic shows LDD-MISFET's on a SOI silicon substrate with five metallization layers and solder bump for flip-chip bonding. Also it shows the section f
18:49, 9 December 2006Thumbnail for version as of 18:49, 9 December 2006550 × 810 (85 KB)Cepheiden{{Information |Description= Schematic structure of a CMOS chip, like it is build in the early 2000s. The grafic shows LDD-MISFET's on a SOI silicon substrate with five metallization layers and solder bumb for flip-chip bonding. Also it shows the section f

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