Draft:Tiny Tera
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| Submission declined on 31 March 2025 by Caleb Stanford (talk). This draft's references do not show that the subject qualifies for a Wikipedia article. In summary, the draft needs multiple published sources that are:
This submission provides insufficient context for those unfamiliar with the subject matter. Please see the guide to writing better articles for information on how to better format your submission. Declined by Caleb Stanford 7 months ago. | |
Comment: is widely recognized as one of the first terabit-class switch prototypes and a landmark in the evolution of high-speed Internet routing.
If true, this would require more substantial justification than the references given. I prefered the previous lead of the article more; the current lead is very promotional, not encyclopedic. Caleb Stanford (talk) 20:46, 31 August 2025 (UTC)
Tiny Tera is widely recognized as one of the first terabit-class switch prototypes and a landmark in the evolution of high-speed Internet routing. Developed in the late 1990s at Stanford University in collaboration with Texas Instruments, it showed that high-performance router cores could be built using commodity CMOS technology rather than specialized optical hardware. The prototype used 32 ports at 10 Gbit/s each for an aggregate bandwidth of 320 Gbit/s, and became a widely cited case study in the design of scalable high-speed switches.[1]
Overview
[edit]Tiny Tera was designed to overcome limitations in router backplanes and memory bandwidth at a time when Internet traffic was growing rapidly. The system used an input-queued switch architecture and a method known as virtual output queuing to mitigate head-of-line blocking, a long-standing problem that reduces throughput in queued switches.[1] A modular “sliced crossbar” design allowed the switch to operate in parallel across many one-bit-wide slices, while a centralized scheduler configured the crossbar every packet time.
A key innovation was the use of the iSLIP scheduling algorithm, a round-robin arbitration method that achieved high throughput and fairness while being simple enough for hardware implementation.[2]
Architecture
[edit]Tiny Tera’s main architectural features included:[1]
- A 32×32 crossbar core implemented as multiple one-bit slices operating in parallel
- Input buffers organized into per-output queues (virtual output queues)
- A centralized scheduler running the iSLIP arbitration algorithm to efficiently match inputs to outputs each cycle[2]
- Support for both unicast and multicast traffic, including fanout-splitting to reduce blocking
- High-speed serial chip-to-chip links to interconnect port cards and the switch core
These design choices allowed the prototype to scale bandwidth while remaining manufacturable with commodity CMOS parts.
Technical Significance
[edit]Tiny Tera demonstrated that a switch core capable of hundreds of gigabits per second could be built with commercially available technology. At the time, most high-end routers were limited by memory or bus bandwidth; Tiny Tera showed that scalable fabrics with efficient scheduling could overcome these limits.[1]
Networking textbooks and reference works have cited Tiny Tera as a pioneering example of packet switch architecture:
- Principles and Practices of Interconnection Networks by William Dally and Brian Towles includes detailed case studies on Tiny Tera’s bit-sliced design and its allocator, situating it alongside industrial designs such as the Cray T3D and IBM Colony router.[3]
- Advanced Router Architectures by Axel Kloth discusses Tiny Tera in the context of scalable router fabrics and high-availability Internet backbones.[4]
These independent sources identify Tiny Tera as a reference design that influenced both academic research and later commercial systems, including large-scale Internet routers from companies such as Cisco and Avici.
Contributors
[edit]The project was led by Stanford professor Nick McKeown, with graduate students Martin Izzard, Adisak Mekkittikul, William Ellersick, and Mark Horowitz contributing to architecture and implementation.[1] Researchers from Texas Instruments’ Communications Lab, including Helen Chang and Ani Anirudhan, collaborated on hardware components and high-speed serial link technology.[1]
Legacy
[edit]Tiny Tera directly influenced subsequent projects at Stanford such as the Stanford Packet Switch and the NetFPGA platform for networking research. Its scheduler design remains a standard reference in computer networking curricula, and the system is frequently cited in academic and industrial literature on crossbar fabrics, switch arbitration, and Internet router scalability.[3]
See also
[edit]- Crossbar switch
- Head-of-line blocking
- Nick McKeown
- Stanford University
- Texas Instruments
- Internet router
References
[edit]- ^ a b c d e f McKeown, Nick; Izzard, Martin; Mekkittikul, Adisak; Ellersick, William; Horowitz, Mark (January–February 1997). "The Tiny Tera: A Packet Switch Core". IEEE Micro. 17 (1): 26–33. doi:10.1109/40.566194. ISSN 0272-1732.
- ^ a b McKeown, Nick; Mekkittikul, Adisak (January–February 1999). "Designing and Implementing a Fast Crossbar Scheduler". IEEE Micro. 19 (1): 58–67. doi:10.1109/40.748793. ISSN 0272-1732.
- ^ a b Dally, William J.; Towles, Brian (2004). Principles and Practices of Interconnection Networks. San Francisco: Morgan Kaufmann. pp. 155–157, 383–385. ISBN 978-0-12-200751-4.
- ^ Kloth, Axel (2006). Advanced Router Architectures. Boca Raton: CRC Press. pp. 215–220. ISBN 978-0-8493-3550-1.